1. Field of the Invention
The present invention generally relates to wiring boards, a mounting structure for electronic components, and semiconductor devices, and more specifically, to an wiring board for mounting electronic components such as for a semiconductor device, the mounting structure for the electronic components, and the semiconductor device.
2. Description of the Related Art
There is a semiconductor device which includes a substrate material that is insulating resin such as glass epoxy resin or the like, a wiring board having a selectively provided conducting layer such as copper (Cu), an external connecting terminal having plural projections (projection form) named as bumps arranged in line on a main plane of a semiconductor integrated circuit device (named as semiconductor element) connected to the conducting layer, and the other main plane of the wiring board having another external connecting terminal selectively provided with spherical electrode terminals on the surfaces of the electrodes. Namely, the semiconductor element is mounted face down on a wiring board. Such a flip-chip mounting structure is formed by the following technique.
A flip-chip mounted substrate includes a semiconductor chip mounted by flip-chip mounting, bumps on the semiconductor chip, a substrate material having a wired layer to be connected to the bumps, metal bumps and the wired layer formed on the substrate material, and a solder resist providing openings located on a part to connect the metal bumps and the wired layer. With the semiconductor chip mounted on the substrate material, an underfill material is supplied into a gap between the semiconductor chip and the substrate material. The openings are formed to be peripheral openings, extended to the outside of the semiconductor chip (see reference 3). The flip-chip mounted semiconductor chip, which has bumps that are provided on the semiconductor chip with solder, is flip-chip mounted on conducting patterns of the wiring board. The conducting patterns are provided with wiring patterns and bumps to be connected to connecting pads. For the line size of the wiring pattern, the size of the connecting pads is designed to become bigger (see reference 4). In a circuit pattern in which a wiring pattern is covered with solder resist, the region of the wiring pattern exposed by the solder resist is used for electrodes of the circuit pattern, wherein the circuit pattern is designed for the electrodes to be included in a maximum line size part (see reference 5).    Reference 1 Japanese Patent Application Publication No. 10-56260    Reference 2 Japanese Patent Application Publication No. 11-214440    Reference 3 Japanese Patent Application Publication No. 11-186322    Reference 4 Japanese Patent Application Publication No. 2000-77471    Reference 5 Japanese Utility Model Registration Application No. 3115062
When a semiconductor element is connected to and mounted on the wiring board by the flip-chip mounting technique described above using the wiring board having the structure described above, it is possible that a bubble (void) is formed at an opening part in the underfill material, particularly at the end part (edge part) of the opening part that is near the center of the wiring board. For this phenomenon an explanation is made with referred to FIG. 1 or FIG. 5.
FIG. 1 is an illustrative drawing showing a plan view of a conventional wiring board on which a semiconductor element is flip-chip mounted. Referring to FIG. 1, a wiring board 10 to be used for the flip-chip mounting includes an insulating resin such as a glass epoxy resin and the like as a substrate material 1; one side of the main plane on it includes a copper (Cu) wiring pattern 2 that is arranged at predetermined places.
Further, the wiring pattern 2 includes bonding electrodes 3. The bonding electrode 3 is formed to be wider than the wiring pattern 2 except where they meet.
Further, a solder resist layer (insulating resin) 5 is formed on the surface including an opening pattern (opening part 4) along a line arranged by plural bonding electrodes 3.
A peripheral part in a longitudinal direction of the opening part 4, for the inner part and the outer part of the wiring board 10, is formed to be almost parallel to the arranged line of the bonding electrodes 3.
In FIG. 1, an alternate long and short dash line X indicates a peripheral area of a semiconductor element 20 (in FIG. 2 or FIG. 5) to be mounted face down on the wiring board 10.
After the semiconductor 20 is mounted face down on the wiring board 10, plural convex shaped external connecting terminals 21 (FIG. 2 or FIG. 5), named as bump that are provided on the main plane of the semiconductor element 20, are connected to the corresponding bonding electrodes 3 of the wiring board 10.
FIG. 2 and FIG. 5 are illustrative drawings to show a flip-chip mounting process where the semiconductor 20 is mounted on the wiring board 10 of FIG. 1.
In each figure, (a) shows an enlarged view of a part encompassed by a broken ellipse-like line in FIG. 1. Each (b) shows a cross-sectional view of the part indicated by a line A-A or a line C-C in (a) of the individual figures, in which the semiconductor element 20 is mounted on the wiring board 10. Each (c) shows a cross-sectional view of the part indicated by a line B-B in (a) of the individual figures.
Further, in each (a), the single-dot broken line X indicates the peripheral area where the semiconductor element 20 is mounted face down on the wiring board 10. The circular single-dot broken lines Y indicate the areas where the convex shaped external connecting terminals 21 of the semiconductor element 20 are connected to the bonding electrodes 3 of the wiring board 10.
Further, the arrows in each FIG. 2 and FIG. 5 indicate the directions of flow for an underfill material 25, as described later.
With reference to FIG. 2, the semiconductor element 20 is flip-chip mounted onto the wiring board 10 as indicated in FIG. 1.
First, on the main plane of the wiring board 10 and at the central part included in the area on which the semiconductor 20 is mounted, the underfill material 25 such as thermosetting adhesive or the like is provided by a coating technique or the like.
Then, for the wiring board 10, a conducting material 6, made of solder including predominantly lead (Sn) is previously provided and formed on the wiring pattern 2.
Further, for the semiconductor element 20, the convex shaped external connecting terminals 21 named as bumps are formed on the electrode pads 22 for the external connecting terminals on the main plane of the semiconductor element 20 by using a ball bonding technique i.e. a wire bonding technique.
Continuing, the semiconductor element 20 is stuck and held on a sticking tool (not shown) that is heated above the melting point of the conducting material 6; and placed facing the wiring board 10 in a bonding position (not shown). A positioning alignment is performed between the convex shaped external connecting terminals 21 and the bonding electrodes 3 of the wiring board 10.
Further, the sticking tool is lowered, and the convex shaped external connecting terminals 21 is contacted on the conducting material 6 provided on the bonding electrodes 3, and then the conducting material 6 is melted.
As a result, the conducting material 6 covers at least the convex shaped part of the convex shape external connecting terminals 21, and this connects the convex shaped external connecting terminals 21 of the semiconductor element 20 and the bonding electrodes 3 of the wiring board 10.
On the other hand, in the process in which the sticking tool is lowered and the convex shaped external connecting terminals 21 contact the conducting material 6 provided on the bonding electrodes 3, the underfill material 25, provided on the wiring board 10, is pushed up by the semiconductor element 20 and starts flowing through the gaps between the semiconductor element 20 and the wiring board 10.
Then in the process in which the convex shaped external connecting terminals 21 of the semiconductor 20 are connected to the bonding electrodes 3 through the conducting material 6, the underfill 25 having started flowing flows toward the peripheral direction of the semiconductor element 20 due to capillarity effect as time passes.
As shown in FIG. 2, at a part of the wiring board 10 where the wiring pattern 2 is not provided, a step is formed corresponding to a formed thickness a of the solder resist layer 5. For another part in which the wiring pattern 2 is formed, another step is formed corresponding to another formed thickness b of the difference between the conducting material 6 deposited and formed on the wiring pattern 2 and the solder resist layer 5.
The step ‘a’ at the part at which the wiring pattern 2 is not provided, is bigger than that of the step ‘b’ in which the wiring pattern 2 is provided (a>b).
Therefore, the distance between the wiring pattern 2 and the underfill material 25 flowing on the solder resist layer 5 is less than that between the substrate material 1 of the wiring board 10 and the underfill material 25 flowing on the solder resist layer 5 in which there is no wiring pattern 2, so that as the flowing of the underfill material 25 continues the flowing velocity of the underfill material 25 on the wiring pattern 2 is faster than that where no wiring pattern 2 exists.
Further, in general, as the wetting velocity of a liquid adhesive on a metal surface is faster than that on a resin surface, the flowing velocity of the underfill material 25 on the wiring pattern 2 is faster than that on the substrate material 1 of the wiring board 10, i.e. no wiring pattern 2 is formed on it.
Therefore, as indicated by the arrows in FIG. 3, the flow of the underfill material 25, flowing into the inner part of the opening part 4 from the peripheral and longitudinal direction of the opening part 4 that is formed to be almost parallel to the arranged direction of the bonding electrodes 3, flows faster on the wiring patten 2 than on the substrate material 1 of the wiring board 10 on which no wiring pattern 2 is formed, and the underfill material 25 flowing on the wiring pattern 2 flows into a region where no wiring pattern 2 is formed.
Thus, the underfill material 25 flowing on the substrate material 1 on the wiring board 10 flows as if being pulled by two flows of the underfill material 25 at both neighboring sides where each side is on the wiring pattern 2, having almost equivalent flowing velocities.
Thereby, while the flow of the underfill material 25 continues, as shown in FIG. 4, due to a difference in flow velocities of the underfill material 25 on parts of the wiring pattern 2 and no wiring pattern 2 and a difference in the flow directions, it is possible to cause a void around an edge of an opening part 4, where the substrate material 1 is exposed and close to the wiring pattern 2 in the opening part 4.
As shown in FIG. 5, when the underfill material 25 flows over almost the whole area of the opening part 4, a filling process of the underfill material 25 is completed and at the same time the underfill material 25 is solidified by the heat provided through the sticking tool (not shown) that is used to mount the semiconductor element 20 on the wiring board 10.
Thus, the convex shaped external connecting terminals 21 and the bonding electrodes 3 of the wiring board 10 are connected by heating solder (soldering), and the underfill material 25, being spread all over the area between the semiconductor element 20 and the wiring board 10, is solidified by heating so that the semiconductor element 20 and the wiring board 10 are stuck together. The connecting areas of the convex shaped external connecting terminals 21 of the semiconductor element 21 are covered by the underfill material 25, wherein the void B is formed and can remain without flowing out at a part around the opening edge of the opening part 4, where the substrate material 1 is exposed and no wiring pattern 2 is on it in the opening part 4.
As is shown in FIG. 5, when the underfill material 25 includes the void B in it, expansion or delamination of the underfill material 25 may be caused when the wiring board 10 with the flip-chip mounted semiconductor element 20 is being mounted on a motherboard or the like by water-vapor expansion due to moisture contained in the void B during a reflow soldering process; and it may cause conducting failure at the connecting areas of the convex shaped external connecting terminals 21.
Further, when the void B is formed near the convex shaped external connecting terminals 21 of the semiconductor 20, the moisture or impurities contained in the void B can affect a leakage current flowing between the adjacent terminals of the convex shaped external connecting terminals 21, and it may cause a degradation of the device characteristics or operating failure of the semiconductor device.
Thus, when the underfill material 25 contains the void B, it is possible that the reliability of the semiconductor device will be degraded.
More particularly, with increasing integration of the semiconductor element 20, the pitch of plural convex shaped external connecting terminals 21 of the semiconductor element 20 becomes smaller; the size of the convex shaped external connecting terminals 21 becomes smaller and decreases the formed height, along with bonding electrodes 3 and the wiring pattern of the wiring board 10. As a result, the heights of the steps a and b (see FIG. 2) in the opening part 4 of the wiring board 10 become more fine and it becomes easier for void B to be trapped in the underfill material 25.
Further, even in the conventional case when such difficulty does not arise from the size of the void B, such difficulty is highly likely to arise when the pitch of plural convex external connecting terminals 21 of the semiconductor element 20 becomes smaller.
When the formed height of the convex shaped external connecting terminals 21 becomes shorter, the gap between the semiconductor element 20 and the wiring board 10 becomes smaller, so that the underfill material 25 becomes thinner. Then, for a size of the void B that does not cause a problem in the conventional case, the same size in the increasing integration leads a larger ratio of the void B to the formed thickness of the underfill material 25; as a result, the problem above becomes likely to happen.
Then, the present invention was made considering the related points above. When an adhesive material is provided into an opening part of an insulating resin layer that is formed on a wiring board, the present invention provides for the adhesive material to flow easily into an exposed part of the substrate material near the wiring pattern in the opening part; it prevents forming a void near the edge of the opening part of the substrate material exposed; even if a void is formed, it provides a wiring board, a mounting structure of electronic components, and semiconductor device having a structure that makes it easier to remove the void.